1. Field of the Invention
The present invention relates to a semiconductor device having a multilayered wiring structure in which an insulating layer and a wiring layer are layered in alternating fashion on a semiconductor substrate.
2. Description of the Related Art
Semiconductor devices having a multilayered wiring structure are known, e.g., a WCSP (Wafer Level Chip Size Package) or the like, in which an insulating layer and a wiring layer are layered in an alternating fashion on a semiconductor substrate. In a multilayered wiring structure, steps are generally generated in the surface of the interlayer insulating film in accordance with the underlying or lower layer-wiring pattern. This causes variability in the shape and in the wiring width of an upper layer-wiring pattern and some countermeasure is thus required. For example, Japanese Laid-open Patent Application Kokai No. 62-104052 (hereinafter referred to as Patent Document 1) discloses a semiconductor device having a structure in which the upper layer-wiring paths are offset by 2 μm or more in the width direction in relation to the lower layer-wiring paths, and a structure in which the width of the lower layer-wiring paths is made greater than the width of the upper layer-wiring paths.